Hardware at the Edge
Course
Will Eatherton of Cisco examines why hardware reliability has become strategically critical in the AI era, covering defensive design, observability at hyperscaler scale and lessons from access to Anthropic's Mythos model.
Sixty-six percent of Meta's AI training job interruptions are caused by hardware failures, and as hyperscalers deploy hundreds of thousands of devices into concentrated environments at unprecedented speed, the consequences of a single hardware flaw have become existential. The leisurely product ramp that allowed issues to surface gradually no longer exists. Observability, once an afterthought, is now the hardest and most critical pillar of hardware engineering.
In this insightful discussion, Will Eatherton of Cisco will discuss:
- Why observability is the most under-weighted pillar of defensive design, and why silent data corruption at scale can cost hundreds of millions of dollars in AI infrastructure;
- How Cisco's six-pillar defensive design framework addresses fault tolerance, foreseeable misuse and design margin before products reach the field;
- What privilege access to Anthropic's Mythos model revealed about long-standing vulnerabilities in widely deployed operating systems.
Here is the course outline:
Hardware at the Edge: Reliability, AI Infrastructure and Defensive Design |
Completion
The following certificates are awarded when the course is completed:
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CPE Credit Certificate |
